feat(esp32s3) add support for esp32s3

.github/workflows/main.yml

@@ -17,7 +17,7 @@ jobs:
     continue-on-error: false
     strategy:
       matrix:
-        target-hardware: [esp32c3,esp32]
+        target-hardware: [esp32c3,esp32,esp32s3]
 
 
     steps:
@@ -77,6 +77,16 @@ jobs:
         command: esptool.py --chip ${{ matrix.target-hardware }} merge_bin -o build/wireless_tools_esp32_full.bin 0x0 build/bootloader/bootloader.bin 0xF000 build/partition_table/partition-table.bin 0x20000 build/wireless_tools_esp32.bin
 
 
+    - name: merge bin files (esp32s3)
+      if: matrix.target-hardware == 'esp32s3'
+      uses: espressif/esp-idf-ci-action@v1
+      with:
+        esp_idf_version: v5.2.1
+        target: ${{ matrix.target-hardware }}
+        path: './'
+        command: esptool.py --chip ${{ matrix.target-hardware }} merge_bin -o build/wireless_tools_esp32_full.bin 0x0 build/bootloader/bootloader.bin 0xF000 build/partition_table/partition-table.bin 0x20000 build/wireless_tools_esp32.bin
+
+
     - name: Upload firmware
       uses: actions/upload-artifact@v2
       with:

README.md

@@ -19,6 +19,7 @@ For Keil users, we now also support [elaphureLink](https://github.com/windowsair
 1. SoC Compatibility
     - [x] ESP32
     - [x] ESP32C3
+    - [x] ESP32S3
     
 2. Debug Communication Mode
     - [x] SWD
@@ -101,6 +102,34 @@ There is built-in ipv4 only mDNS server. You can access the device using `dap.lo
 | TVCC               | 3V3     |
 | GND                | GND     |
 
+</details>
+
+<details>
+<summary>ESP32S3</summary>
+
+| SWD            |        |
+|----------------|--------|
+| SWCLK          | GPIO12 |
+| SWDIO          | GPIO11 |
+| TVCC           | 3V3    |
+| GND            | GND    |
+
+
+--------------
+
+
+| JTAG               |        |
+|--------------------|--------|
+| TCK                | GPIO12 |
+| TMS                | GPIO11 |
+| TDI                | GPIO10 |
+| TDO                | GPIO9  |
+| nTRST \(optional\) | GPIO14 |
+| nRESET             | GPIO13 |
+| TVCC               | 3V3    |
+| GND                | GND    |
+
+
 </details>
 
 

README_CN.md

@@ -15,6 +15,7 @@
 1. 支持的ESP芯片
     - [x] ESP32
     - [x] ESP32C3
+    - [x] ESP32S3
 
 2. 支持的调试接口：
     - [x] SWD
@@ -95,6 +96,32 @@
 
 </details>
 
+<details>
+<summary>ESP32S3</summary>
+
+| SWD            |        |
+|----------------|--------|
+| SWCLK          | GPIO12 |
+| SWDIO          | GPIO11 |
+| TVCC           | 3V3    |
+| GND            | GND    |
+
+
+--------------
+
+
+| JTAG               |        |
+|--------------------|--------|
+| TCK                | GPIO12 |
+| TMS                | GPIO11 |
+| TDI                | GPIO10 |
+| TDO                | GPIO9  |
+| nTRST \(optional\) | GPIO14 |
+| nRESET             | GPIO13 |
+| TVCC               | 3V3    |
+| GND                | GND    |
+
+
 
 ----
 

components/DAP/DAP_config.h

@@ -60,6 +60,7 @@
   #include "esp8266/pin_mux_register.h"
 #elif defined CONFIG_IDF_TARGET_ESP32
 #elif defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined CONFIG_IDF_TARGET_ESP32S3
 #else
   #error unknown hardware
 #endif
@@ -99,6 +100,8 @@ This information includes:
 #elif defined CONFIG_IDF_TARGET_ESP32C3
   #define CPU_CLOCK 16000000
   // <<<<<<<<<<<<<<<<<<<<<<<<<<<<<160MHz
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+  #define CPU_CLOCK 240000000
 #endif
 
 
@@ -374,7 +377,19 @@ __STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) {
 
   #define PIN_LED_CONNECTED _ // won't be used
   #define PIN_LED_RUNNING _ // won't be used
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+  #define PIN_SWDIO _      // SPI MISO
+  #define PIN_SWDIO_MOSI 11 // SPI MOSI
+  #define PIN_SWCLK 12
+  #define PIN_TDO 9        // device TDO -> Host Data Input
+  #define PIN_TDI 10
+  #define PIN_nTRST 14       // optional
+  #define PIN_nRESET 13
 
+  #define PIN_LED_CONNECTED _ // won't be used
+  #define PIN_LED_RUNNING _ // won't be used
+#else
+#error "not a supported target"
 #endif
 
 
@@ -534,6 +549,29 @@ __STATIC_INLINE void PORT_JTAG_SETUP(void)
   GPIO_PULL_UP_ONLY_SET(PIN_nTRST);
   GPIO_PULL_UP_ONLY_SET(PIN_nRESET);
 }
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+__STATIC_INLINE void PORT_JTAG_SETUP(void)
+{
+	// set TCK, TMS pin
+
+	// PIN_TDO output disable
+	gpio_ll_output_disable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_TDO);
+	// PIN_TDO input enable
+	gpio_ll_input_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_TDO);
+
+	// PIN_TDI output
+	gpio_ll_output_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_TDI);
+	gpio_ll_od_disable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_TDI);
+	gpio_ll_pulldown_dis(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_TDI);
+
+	gpio_ll_output_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_nTRST);
+	gpio_ll_od_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_nTRST);
+	gpio_ll_output_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_nRESET);
+	gpio_ll_od_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_nRESET);
+
+	GPIO_PULL_UP_ONLY_SET(PIN_nTRST);
+	GPIO_PULL_UP_ONLY_SET(PIN_nRESET);
+}
 #endif
 
 /**
@@ -584,6 +622,11 @@ __STATIC_INLINE void PORT_OFF(void)
 
   // gpio_set_pull_mode(PIN_nTRST, GPIO_PULLUP_ONLY);
   GPIO_PULL_UP_ONLY_SET(PIN_nRESET);
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+	gpio_ll_output_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_nRESET);
+	gpio_ll_od_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_nRESET);
+	GPIO_PULL_UP_ONLY_SET(PIN_nRESET);
+	gpio_ll_set_level(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_nRESET, 1);
 #endif
 }
 
@@ -727,6 +770,10 @@ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
   // Note that the input of esp32c3 is not always connected.
   PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[PIN_SWDIO_MOSI]);
   GPIO.out_w1ts.out_w1ts = (0x1 << PIN_SWDIO_MOSI);
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+	// Note that the input is not always connected.
+	gpio_ll_input_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_SWDIO_MOSI);
+	gpio_ll_set_level(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_SWDIO_MOSI, 1);
 #endif
 }
 
@@ -775,7 +822,7 @@ __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
   return READ_PERI_REG(RTC_GPIO_IN_DATA) & 0x1;
 #elif defined CONFIG_IDF_TARGET_ESP32
   return ((GPIO.in >> PIN_TDO) & 0x1) ? 1 : 0;
-#elif defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP32S3
   return GPIO_GET_LEVEL(PIN_TDO);
 #endif
 }
@@ -836,6 +883,8 @@ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
     GPIO.enable_w1tc |= (0x01 << PIN_nRESET);
 #elif defined CONFIG_IDF_TARGET_ESP32C3
     GPIO.enable_w1tc.enable_w1tc |= (0x01 << PIN_nRESET);
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+	gpio_ll_output_disable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_nRESET);
 #endif
   }
   else
@@ -845,6 +894,8 @@ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
     GPIO.enable_w1ts |= (0x01 << PIN_nRESET);
 #elif defined CONFIG_IDF_TARGET_ESP32C3
     GPIO.enable_w1ts.enable_w1ts |= (0x01 << PIN_nRESET);
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+    gpio_ll_output_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_nRESET);
 #endif
     GPIO_SET_LEVEL_LOW(PIN_nRESET);
   }

components/DAP/cmsis-dap/include/DAP.h

@@ -345,7 +345,7 @@ extern void     DAP_Setup (void);
       ;
   }
 #else
-  #if defined CONFIG_IDF_TARGET_ESP8266 || CONFIG_IDF_TARGET_ESP32
+  #if defined CONFIG_IDF_TARGET_ESP8266 || defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S3
 __STATIC_FORCEINLINE void PIN_DELAY_SLOW(int32_t delay)
 {
   __asm__ volatile(

components/DAP/cmsis-dap/include/gpio_common.h

@@ -31,9 +31,10 @@
         #include "soc/soc/esp32/include/soc/spi_reg.h"
     #endif
     #include "hal/gpio_types.h"
-#elif defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
     #include "soc/gpio_struct.h"
     #include "hal/gpio_ll.h"
+	#include "hal/gpio_hal.h"
     #include "hal/clk_gate_ll.h"
     #include "soc/gpio_struct.h"
     #include "soc/dport_access.h"

components/DAP/cmsis-dap/include/gpio_op.h

@@ -53,6 +53,11 @@ __STATIC_INLINE __UNUSED void GPIO_FUNCTION_SET(int io_num)
   }
   PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_num], PIN_FUNC_GPIO);
 }
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+__STATIC_INLINE __UNUSED void GPIO_FUNCTION_SET(int io_num)
+{
+  gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[io_num], PIN_FUNC_GPIO);
+}
 #endif
 
 
@@ -77,6 +82,13 @@ __STATIC_INLINE __UNUSED void GPIO_SET_DIRECTION_NORMAL_OUT(int io_num)
     // PP out
     GPIO.pin[io_num].pad_driver = 0;
 }
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+__STATIC_INLINE __UNUSED void GPIO_SET_DIRECTION_NORMAL_OUT(int io_num)
+{
+	gpio_ll_output_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), io_num);
+	// PP out
+	gpio_ll_od_disable(GPIO_HAL_GET_HW(GPIO_PORT_0), io_num);
+}
 #endif
 
 
@@ -90,14 +102,14 @@ __STATIC_INLINE __UNUSED void GPIO_SET_LEVEL_LOW(int io_num)
 {
   GPIO.out_w1tc |= (0x1 << io_num);
 }
-#elif defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP32S3
 __STATIC_INLINE __UNUSED void GPIO_SET_LEVEL_HIGH(int io_num)
 {
-  gpio_ll_set_level(&GPIO, io_num, 1);
+  gpio_ll_set_level(GPIO_HAL_GET_HW(GPIO_PORT_0), io_num, 1);
 }
 __STATIC_INLINE __UNUSED void GPIO_SET_LEVEL_LOW(int io_num)
 {
-  gpio_ll_set_level(&GPIO, io_num, 0);
+  gpio_ll_set_level(GPIO_HAL_GET_HW(GPIO_PORT_0), io_num, 0);
 }
 #endif
 
@@ -107,10 +119,10 @@ __STATIC_INLINE __UNUSED int GPIO_GET_LEVEL(int io_num)
 {
   return ((GPIO.in >> io_num) & 0x1) ? 1 : 0;
 }
-#elif defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP32S3
 __STATIC_INLINE __UNUSED int GPIO_GET_LEVEL(int io_num)
 {
-  return gpio_ll_get_level(&GPIO, io_num);
+  return gpio_ll_get_level(GPIO_HAL_GET_HW(GPIO_PORT_0), io_num);
 }
 #endif
 
@@ -125,6 +137,14 @@ __STATIC_INLINE __UNUSED void GPIO_PULL_UP_ONLY_SET(int io_num)
   // enable pull up
   REG_SET_BIT(GPIO_PIN_MUX_REG[io_num], FUN_PU);
 }
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+__STATIC_INLINE __UNUSED void GPIO_PULL_UP_ONLY_SET(int io_num)
+{
+	// disable pull down
+	gpio_ll_pulldown_dis(GPIO_HAL_GET_HW(GPIO_PORT_0), io_num);
+	// enable pull up
+	gpio_ll_pullup_en(GPIO_HAL_GET_HW(GPIO_PORT_0), io_num);
+}
 #elif defined CONFIG_IDF_TARGET_ESP8266
 __STATIC_INLINE __UNUSED void GPIO_PULL_UP_ONLY_SET(int io_num)
 {

components/DAP/cmsis-dap/source/DAP.c

@@ -437,7 +437,7 @@ static uint32_t DAP_SWJ_Clock(const uint8_t *request, uint8_t *response) {
 
 #ifdef CONFIG_IDF_TARGET_ESP8266
   #define BUS_CLOCK_FIXED 80000000
-#elif defined CONFIG_IDF_TARGET_ESP32
+#elif defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S3
   #define BUS_CLOCK_FIXED 100000000
 #elif defined CONFIG_IDF_TARGET_ESP32C3
   #define BUS_CLOCK_FIXED 80000000

components/DAP/cmsis-dap/source/SW_DP.c

@@ -292,7 +292,7 @@ static uint8_t SWD_Transfer_SPI (uint32_t request, uint32_t *data) {
     else if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) {
 #if defined CONFIG_IDF_TARGET_ESP8266 || defined CONFIG_IDF_TARGET_ESP32
       DAP_SPI_Generate_Cycle(1);
-#elif defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP32S3
       DAP_SPI_Fast_Cycle();
 #endif
 

components/DAP/cmsis-dap/source/spi_op.c

@@ -29,6 +29,8 @@
     #define DAP_SPI SPI2
 #elif defined CONFIG_IDF_TARGET_ESP32C3
     #define DAP_SPI GPSPI2
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+	#define DAP_SPI GPSPI2
 #else
     #error unknown hardware
 #endif
@@ -52,7 +54,7 @@
             while (DAP_SPI.cmd.usr) continue;      \
         } while(0)
 
-#elif defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP32S3
     #define SET_MOSI_BIT_LEN(x) DAP_SPI.ms_dlen.ms_data_bitlen = x
     #define SET_MISO_BIT_LEN(x) DAP_SPI.ms_dlen.ms_data_bitlen = x
     #define START_AND_WAIT_SPI_TRANSMISSION_DONE() \
@@ -207,7 +209,7 @@ __FORCEINLINE void DAP_SPI_Send_Header(const uint8_t packetHeaderData, uint8_t *
     dataBuf = DAP_SPI.data_buf[0];
     *ack = (dataBuf >> 1) & 0b111;
 } // defined CONFIG_IDF_TARGET_ESP8266 || defined CONFIG_IDF_TARGET_ESP32
-#elif defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP32S3
 __FORCEINLINE void DAP_SPI_Send_Header(const uint8_t packetHeaderData, uint8_t *ack, uint8_t TrnAfterACK)
 {
     uint32_t dataBuf;
@@ -297,7 +299,7 @@ __FORCEINLINE void DAP_SPI_Write_Data(uint32_t data, uint8_t parity)
 
     START_AND_WAIT_SPI_TRANSMISSION_DONE();
 }
-#elif defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP32S3
 __FORCEINLINE void DAP_SPI_Write_Data(uint32_t data, uint8_t parity)
 {
     DAP_SPI.user.usr_mosi = 1;
@@ -314,7 +316,7 @@ __FORCEINLINE void DAP_SPI_Write_Data(uint32_t data, uint8_t parity)
 #endif
 
 
-#if defined CONFIG_IDF_TARGET_ESP8266 || defined CONFIG_IDF_TARGET_ESP32
+#if defined CONFIG_IDF_TARGET_ESP8266 || defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S3
 /**
  * @brief Generate Clock Cycle
  *
@@ -345,7 +347,7 @@ __FORCEINLINE void DAP_SPI_Generate_Cycle(uint8_t num)
 }
 #endif
 
-#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32C3
+#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP32S3
 /**
  * @brief Quickly generate 1 clock
  *

components/DAP/cmsis-dap/source/spi_switch.c

@@ -18,6 +18,7 @@
 #include "cmsis-dap/include/cmsis_compiler.h"
 #include "cmsis-dap/include/spi_switch.h"
 #include "cmsis-dap/include/gpio_common.h"
+#include "DAP_config.h"
 
 #ifdef CONFIG_IDF_TARGET_ESP8266
     #define DAP_SPI SPI1
@@ -29,6 +30,8 @@
     #define SPI_LL_RST_MASK (SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST)
 #elif defined CONFIG_IDF_TARGET_ESP32C3
     #define DAP_SPI GPSPI2
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+    #define DAP_SPI GPSPI2
 #else
     #error unknown hardware
 #endif
@@ -351,6 +354,92 @@ void DAP_SPI_Init()
     DAP_SPI.user.usr_command = 0;
     DAP_SPI.user.usr_addr = 0;
 }
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+void DAP_SPI_Init()
+{
+	periph_ll_enable_clk_clear_rst(PERIPH_SPI2_MODULE);
+
+	// In esp32, the driving of GPIO should be stopped,
+	// otherwise there will be issue in the spi
+	gpio_ll_set_level(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_SWDIO_MOSI, 0);
+	gpio_ll_set_level(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_SWCLK, 0);
+
+	// We will use IO_MUX to get the maximum speed.
+	gpio_ll_iomux_in(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_SWCLK,FSPICLK_IN_IDX);
+	gpio_ll_iomux_out(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_SWCLK, FUNC_GPIO12_FSPICLK, 0);
+
+	gpio_ll_iomux_in(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_SWDIO_MOSI,FSPID_IN_IDX);
+	gpio_ll_iomux_out(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_SWDIO_MOSI, FUNC_GPIO11_FSPID, 0);
+
+//	// Not using DMA
+	DAP_SPI.user.usr_conf_nxt = 0;
+	DAP_SPI.slave.usr_conf = 0;
+	DAP_SPI.dma_conf.dma_rx_ena = 0;
+	DAP_SPI.dma_conf.dma_tx_ena = 0;
+
+	// Set to Master mode
+	DAP_SPI.slave.slave_mode = false;
+
+	// use all 64 bytes of the buffer
+	DAP_SPI.user.usr_mosi_highpart = false;
+	DAP_SPI.user.usr_miso_highpart = false;
+
+	// Disable cs pin
+	DAP_SPI.user.cs_setup = false;
+	DAP_SPI.user.cs_hold = false;
+
+	// Disable CS signal
+	DAP_SPI.misc.cs0_dis = 1;
+	DAP_SPI.misc.cs1_dis = 1;
+	DAP_SPI.misc.cs2_dis = 1;
+	DAP_SPI.misc.cs3_dis = 1;
+	DAP_SPI.misc.cs4_dis = 1;
+	DAP_SPI.misc.cs5_dis = 1;
+
+	// Duplex transmit
+	DAP_SPI.user.doutdin = false;  // half dulex
+
+	// Set data bit order
+	DAP_SPI.ctrl.wr_bit_order = 1;   // SWD -> LSB
+	DAP_SPI.ctrl.rd_bit_order = 1;   // SWD -> LSB
+
+	// Set dummy
+	DAP_SPI.user.usr_dummy = 0; // not use
+
+	// Set spi clk: 40Mhz 50% duty
+	// CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI1_CLK_EQU_SYS_CLK);
+
+	// See TRM `SPI_CLOCK_REG`
+	DAP_SPI.clock.clk_equ_sysclk = false;
+	DAP_SPI.clock.clkdiv_pre = 0;
+	DAP_SPI.clock.clkcnt_n = SPI_40MHz_DIV - 1;
+	DAP_SPI.clock.clkcnt_h = SPI_40MHz_DIV / 2 - 1;
+	DAP_SPI.clock.clkcnt_l = SPI_40MHz_DIV - 1;
+
+	// MISO delay setting
+	DAP_SPI.user.rsck_i_edge = true;
+	DAP_SPI.din_mode.din0_mode = 0;
+	DAP_SPI.din_mode.din1_mode = 0;
+	DAP_SPI.din_mode.din2_mode = 0;
+	DAP_SPI.din_mode.din3_mode = 0;
+	DAP_SPI.din_num.din0_num = 0;
+	DAP_SPI.din_num.din1_num = 0;
+	DAP_SPI.din_num.din2_num = 0;
+	DAP_SPI.din_num.din3_num = 0;
+
+	// Set the clock polarity and phase CPOL = 1, CPHA = 0
+	DAP_SPI.misc.ck_idle_edge = 1;  // HIGH while idle
+	DAP_SPI.user.ck_out_edge = 0;
+
+	// enable spi clock
+	DAP_SPI.clk_gate.clk_en = 1;
+	DAP_SPI.clk_gate.mst_clk_active = 1;
+	DAP_SPI.clk_gate.mst_clk_sel = 1;
+
+	// No command and addr for now
+	DAP_SPI.user.usr_command = 0;
+	DAP_SPI.user.usr_addr = 0;
+}
 #endif
 
 
@@ -416,6 +505,21 @@ __FORCEINLINE void DAP_SPI_Deinit()
     GPIO.enable_w1ts.enable_w1ts |= (0x1 << 7);
     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[7]);
 }
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+__FORCEINLINE void DAP_SPI_Deinit()
+{
+	gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[PIN_SWCLK], PIN_FUNC_GPIO);
+	gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[PIN_SWDIO_MOSI], PIN_FUNC_GPIO); // MOSI
+	//PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[12], PIN_FUNC_GPIO); // MISO
+
+	// enable SWCLK output
+	gpio_ll_output_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_SWCLK);
+
+	// enable MOSI output & input
+//	gpio_ll_output_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_SWDIO_MOSI);
+	GPIO.enable_w1ts |= (0x1 << PIN_SWDIO_MOSI);
+	gpio_ll_input_enable(GPIO_HAL_GET_HW(GPIO_PORT_0), PIN_SWDIO_MOSI);
+}
 #endif
 
 
@@ -458,6 +562,25 @@ __FORCEINLINE void DAP_SPI_Release()
 {
     PIN_FUNC_SELECT(IO_MUX_GPIO6_REG, FUNC_MTCK_GPIO6);
 }
+#elif defined CONFIG_IDF_TARGET_ESP32S3
+/**
+ * @brief Gain control of SPI
+ *
+ */
+__FORCEINLINE void DAP_SPI_Acquire()
+{
+	gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[PIN_SWCLK], FUNC_GPIO12_FSPICLK);
+}
+
+
+/**
+ * @brief Release control of SPI
+ *
+ */
+__FORCEINLINE void DAP_SPI_Release()
+{
+	gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[PIN_SWCLK], FUNC_GPIO12_GPIO12);
+}
 #endif
 /**
  * @brief Use SPI acclerate

sdkconfig.defaults.esp32c3

@@ -302,7 +302,6 @@ CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y
 # CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set
 # CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set
 # CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set
-# CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 is not set
 # end of ADC and ADC Calibration
 
 #
@@ -354,7 +353,7 @@ CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH=y
 #
 # HTTP Server
 #
-CONFIG_HTTPD_MAX_REQ_HDR_LEN=512
+CONFIG_HTTPD_MAX_REQ_HDR_LEN=1024
 CONFIG_HTTPD_MAX_URI_LEN=256
 CONFIG_HTTPD_ERR_RESP_NO_DELAY=y
 CONFIG_HTTPD_PURGE_BUF_LEN=32
@@ -417,8 +416,6 @@ CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY=0
 CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS=y
 # end of Sleep Config
 
-CONFIG_ESP_SLEEP_SYSTIMER_STALL_WORKAROUND=y
-
 #
 # RTC Clock Config
 #
@@ -604,9 +601,9 @@ CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
 CONFIG_ESP_WIFI_ENABLED=y
 # CONFIG_ESP_WIFI_CSI_ENABLED is not set
 CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y
-CONFIG_ESP_WIFI_TX_BA_WIN=8
+CONFIG_ESP_WIFI_TX_BA_WIN=6
 CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y
-CONFIG_ESP_WIFI_RX_BA_WIN=8
+CONFIG_ESP_WIFI_RX_BA_WIN=6
 CONFIG_ESP_WIFI_NVS_ENABLED=y
 CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752
 CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32