775 lines
24 KiB
C
775 lines
24 KiB
C
/*
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* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* ----------------------------------------------------------------------
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*
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* $Date: 1. December 2017
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* $Revision: V2.0.0
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*
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* Project: CMSIS-DAP Configuration
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* Title: DAP_config.h CMSIS-DAP Configuration File (Template)
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*
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*---------------------------------------------------------------------------*/
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#ifndef __DAP_CONFIG_H__
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#define __DAP_CONFIG_H__
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#include <stdint.h>
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#include <string.h>
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#include "cmsis_compiler.h"
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#include "gpio.h"
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#include "gpio_struct.h"
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#include "timer_struct.h"
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#include "esp8266/pin_mux_register.h"
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#include "spi_switch.h"
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#include "dap_configuration.h"
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//**************************************************************************************************
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/**
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\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
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\ingroup DAP_ConfigIO_gr
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@{
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Provides definitions about the hardware and configuration of the Debug Unit.
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This information includes:
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- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
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- Debug Unit Identification strings (Vendor, Product, Serial Number).
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- Debug Unit communication packet size.
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- Debug Access Port supported modes and settings (JTAG/SWD and SWO).
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- Optional information about a connected Target Device (for Evaluation Boards).
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*/
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//#ifdef _RTE_
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//#include "RTE_Components.h"
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//#include CMSIS_device_header
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//#else
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//#include "device.h" // Debug Unit Cortex-M Processor Header File
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//#endif
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/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
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/// This value is used to calculate the SWD/JTAG clock speed.
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#define CPU_CLOCK 160000000 ///< Specifies the CPU Clock in Hz.
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// <<<<<<<<<<<<<<<<<<<<<<<<<<<<<160MHz
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// This value is used to replace the largest 10MHZ speed clock in Keil
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#define MAX_USER_CLOCK 16000000 ///< Specifies the max Debug Clock in Hz.
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/// Number of processor cycles for I/O Port write operations.
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/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
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/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
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/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
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/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
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/// required.
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#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
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/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
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/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
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#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available.
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/// Indicate that JTAG communication mode is available at the Debug Port.
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/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
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#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
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/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
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/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
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#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain.
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/// Default communication mode on the Debug Access Port.
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/// Used for the command \ref DAP_Connect when Port Default mode is selected.
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#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
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/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
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/// Used to initialize the default SWD/JTAG clock frequency.
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/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
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#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
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// <<<<<<<<<<<<<<<<<<<<<<<<<<<<<1MHz
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/// Maximum Package Buffers for Command and Response data.
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/// This configuration settings is used to optimize the communication performance with the
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/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
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/// setting can be reduced (valid range is 1 .. 255).
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#define DAP_PACKET_COUNT 255 ///< Specifies number of packets buffered.
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/// Indicate that UART Serial Wire Output (SWO) trace is available.
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/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
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#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available.
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/// Maximum SWO UART Baudrate.
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#define SWO_UART_MAX_BAUDRATE (115200U * 40U) ///< SWO UART Maximum Baudrate in Hz.
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// <<<<<<<<<<<<<<<<<<<<<<<<<<<<< 5MHz
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//// TODO: uncertain value
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/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
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/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
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#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available.
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/// SWO Trace Buffer Size.
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#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n).
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/// SWO Streaming Trace.
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#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
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/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
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#define TIMESTAMP_CLOCK 5000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
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// <<<<<<<<<<<<<<<<<<<<<5MHz
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/// Debug Unit is connected to fixed Target Device.
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/// The Debug Unit may be part of an evaluation board and always connected to a fixed
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/// known device. In this case a Device Vendor and Device Name string is stored which
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/// may be used by the debugger or IDE to configure device parameters.
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#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
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#if TARGET_DEVICE_FIXED
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#define TARGET_DEVICE_VENDOR "ARM" ///< String indicating the Silicon Vendor
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#define TARGET_DEVICE_NAME "Cortex-M4" ///< String indicating the Target Device
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#endif
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/**
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* @brief Get Vendor ID string.
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*
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* @param str Pointer to buffer to store the string.
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* @return String length.
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*/
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__STATIC_INLINE uint8_t DAP_GetVendorString(char *str)
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{
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////TODO: fill this
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// In fact, Keil can get the corresponding information through USB
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// without filling in this information.
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// (void)str;
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strcpy(str, "windowsair");
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return (sizeof("windowsair"));
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}
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/**
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* @brief Get Product ID string.
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*
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* @param str Pointer to buffer to store the string.
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* @return String length.
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*/
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__STATIC_INLINE uint8_t DAP_GetProductString(char *str)
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{
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//(void)str;
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strcpy(str, "CMSIS-DAP v2");
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return (sizeof("CMSIS-DAP v2"));
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}
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/**
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* @brief Get Serial Number string.
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*
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* @param str Pointer to buffer to store the string.
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* @return String length.
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*/
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__STATIC_INLINE uint8_t DAP_GetSerNumString(char *str)
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{
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strcpy(str, "1234");
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return (sizeof("1234"));
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}
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///@}
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// Modify your pins here
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// ATTENTION: DO NOT USE RTC GPIO16
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#define PIN_SWDIO 12
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#define PIN_SWDIO_MOSI 13 // SPI MOSI
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#define PIN_SWCLK 14
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#define PIN_TDO 4
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#define PIN_TDI 0
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#define PIN_nTRST 0 // optional
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#define PIN_nRESET 5
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// LED_BUILTIN
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#define PIN_LED_CONNECTED 2
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// LED_BUILTIN
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#define PIN_LED_RUNNING 15
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//**************************************************************************************************
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/**
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\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
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\ingroup DAP_ConfigIO_gr
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@{
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Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
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and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
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interface of a device. The following I/O Pins are provided:
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JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
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---------------------------- | -------------------- | ---------------------------------------------
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TCK: Test Clock | SWCLK: Clock | Output Push/Pull
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TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
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TDI: Test Data Input | | Output Push/Pull
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TDO: Test Data Output | | Input
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nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
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nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
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DAP Hardware I/O Pin Access Functions
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-------------------------------------
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The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
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these I/O Pins.
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For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
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This functions are provided to achieve faster I/O that is possible with some advanced GPIO
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peripherals that can independently write/read a single I/O pin without affecting any other pins
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of the same I/O port. The following SWDIO I/O Pin functions are provided:
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- \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
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- \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
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- \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
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- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
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*/
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/**
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* @brief Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
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* Configures the DAP Hardware I/O pins for JTAG mode:
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* - TCK, TMS, TDI, nTRST, nRESET to ***output*** mode and set to high level.
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* - TDO to ***input*** mode.
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*
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*/
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__STATIC_INLINE void PORT_JTAG_SETUP(void)
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{
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gpio_pin_reg_t pin_reg;
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// gpio_set_direction(PIN_SWCLK, GPIO_MODE_OUTPUT);
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// gpio_set_direction(PIN_SWDIO, GPIO_MODE_OUTPUT);
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GPIO.enable_w1ts |= (0x1 << PIN_SWCLK);
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GPIO.pin[PIN_SWCLK].driver = 0;
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(PIN_SWCLK));
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pin_reg.pullup = 0;
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WRITE_PERI_REG(GPIO_PIN_REG(PIN_SWCLK), pin_reg.val);
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GPIO.enable_w1ts |= (0x1 << PIN_SWDIO);
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GPIO.pin[PIN_SWDIO].driver = 0;
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(PIN_SWDIO));
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pin_reg.pullup = 0;
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WRITE_PERI_REG(GPIO_PIN_REG(PIN_SWDIO), pin_reg.val);
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// gpio_set_direction(PIN_TDO, GPIO_MODE_DEF_INPUT);
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GPIO.enable_w1tc |= (0x1 << PIN_TDO);
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GPIO.pin[PIN_TDO].driver = 0;
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(PIN_TDO));
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pin_reg.pullup = 0;
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WRITE_PERI_REG(GPIO_PIN_REG(PIN_TDO), pin_reg.val);
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// gpio_set_direction(PIN_TDI, GPIO_MODE_OUTPUT);
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GPIO.enable_w1ts |= (0x1 << PIN_TDI);
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GPIO.pin[PIN_TDI].driver = 0;
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(PIN_TDI));
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pin_reg.pullup = 0;
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WRITE_PERI_REG(GPIO_PIN_REG(PIN_TDI), pin_reg.val);
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// gpio_set_direction(PIN_nTRST, GPIO_MODE_OUTPUT_OD);
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// gpio_set_direction(PIN_nRESET, GPIO_MODE_OUTPUT_OD);
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GPIO.enable_w1tc |= (0x1 << PIN_nTRST);
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GPIO.pin[PIN_nTRST].driver = 1;
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GPIO.enable_w1tc |= (0x1 << PIN_nRESET);
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GPIO.pin[PIN_nRESET].driver = 1;
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// gpio_set_pull_mode(PIN_nTRST, GPIO_PULLUP_ONLY);
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// gpio_set_pull_mode(PIN_nRESET, GPIO_PULLUP_ONLY);
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(PIN_nTRST));
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pin_reg.pullup = 1;
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WRITE_PERI_REG(GPIO_PIN_REG(PIN_nTRST), pin_reg.val);
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(PIN_nRESET));
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pin_reg.pullup = 1;
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WRITE_PERI_REG(GPIO_PIN_REG(PIN_nRESET), pin_reg.val);
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}
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/**
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* @brief Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
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* Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
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* - SWCLK, SWDIO, nRESET to output mode and set to default high level.
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* - TDI, nTRST to HighZ mode (pins are unused in SWD mode).
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*
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*/
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__STATIC_INLINE void PORT_SWD_SETUP(void)
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{
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gpio_pin_reg_t pin_reg;
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// PIN_SWCLK -> OUTPUT
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// PIN_SWDIO -> OUTPUT
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// GPIO.enable_w1ts |= (0x1 << PIN_SWCLK);
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// GPIO.pin[PIN_SWCLK].driver = 0;
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// pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(PIN_SWCLK));
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// pin_reg.pullup = 0;
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// WRITE_PERI_REG(GPIO_PIN_REG(PIN_SWCLK), pin_reg.val);
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// GPIO.enable_w1ts |= (0x1 << PIN_SWDIO);
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// GPIO.pin[PIN_SWDIO].driver = 0;
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// pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(PIN_SWDIO));
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// pin_reg.pullup = 0;
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// WRITE_PERI_REG(GPIO_PIN_REG(PIN_SWDIO), pin_reg.val);
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DAP_SPI_Disable();
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GPIO.out_w1tc |= (0x1 << PIN_SWCLK);
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GPIO.out_w1ts |= (0x1 << PIN_SWDIO_MOSI);
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// gpio_set_direction(PIN_TDO, GPIO_MODE_DEF_INPUT);
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GPIO.enable_w1tc |= (0x1 << PIN_TDO);
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GPIO.pin[PIN_TDO].driver = 0;
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(PIN_TDO));
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pin_reg.pullup = 0;
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WRITE_PERI_REG(GPIO_PIN_REG(PIN_TDO), pin_reg.val);
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// gpio_set_direction(PIN_TDI, GPIO_MODE_OUTPUT);
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GPIO.enable_w1ts |= (0x1 << PIN_TDI);
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GPIO.pin[PIN_TDI].driver = 0;
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(PIN_TDI));
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pin_reg.pullup = 0;
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WRITE_PERI_REG(GPIO_PIN_REG(PIN_TDI), pin_reg.val);
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// gpio_set_direction(PIN_nTRST, GPIO_MODE_OUTPUT_OD);
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// gpio_set_direction(PIN_nRESET, GPIO_MODE_OUTPUT_OD);
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GPIO.enable_w1tc |= (0x1 << PIN_nTRST);
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GPIO.pin[PIN_nTRST].driver = 1;
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GPIO.enable_w1tc |= (0x1 << PIN_nRESET);
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GPIO.pin[PIN_nRESET].driver = 1;
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// gpio_set_pull_mode(PIN_nTRST, GPIO_PULLUP_ONLY);
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// gpio_set_pull_mode(PIN_nRESET, GPIO_PULLUP_ONLY);
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(PIN_nTRST));
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pin_reg.pullup = 1;
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WRITE_PERI_REG(GPIO_PIN_REG(PIN_nTRST), pin_reg.val);
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(PIN_nRESET));
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pin_reg.pullup = 1;
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WRITE_PERI_REG(GPIO_PIN_REG(PIN_nRESET), pin_reg.val);
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}
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/**
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* @brief Disable JTAG/SWD I/O Pins.
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* Disables the DAP Hardware I/O pins which configures:
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* - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
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*
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*/
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__STATIC_INLINE void PORT_OFF(void)
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{
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// Will be called when the DAP disconnected
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// gpio_set_direction(PIN_SWCLK, GPIO_MODE_DEF_DISABLE);
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// gpio_set_direction(PIN_SWDIO, GPIO_MODE_DEF_DISABLE);
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// gpio_set_direction(PIN_TDO, GPIO_MODE_DEF_DISABLE);
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// gpio_set_direction(PIN_TDI, GPIO_MODE_DEF_DISABLE);
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// gpio_set_direction(PIN_nTRST, GPIO_MODE_DEF_DISABLE);
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// gpio_set_direction(PIN_nRESET, GPIO_MODE_DEF_DISABLE);
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// GPIO.pin[PIN_SWCLK].driver = 0;
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// GPIO.enable_w1tc |= (0x1 << PIN_SWCLK);
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// GPIO.pin[PIN_SWDIO].driver = 0;
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// GPIO.enable_w1tc |= (0x1 << PIN_SWDIO);
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// GPIO.pin[PIN_SWDIO].driver = 0;
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// GPIO.enable_w1tc |= (0x1 << PIN_SWDIO_MOSI);
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DAP_SPI_Disable();
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GPIO.out_w1tc |= (0x1 << PIN_SWCLK);
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GPIO.out_w1ts |= (0x1 << PIN_SWDIO_MOSI);
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GPIO.pin[PIN_TDO].driver = 0;
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GPIO.enable_w1tc |= (0x1 << PIN_TDO);
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GPIO.pin[PIN_TDI].driver = 0;
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GPIO.enable_w1tc |= (0x1 << PIN_TDI);
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GPIO.pin[PIN_nTRST].driver = 0;
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GPIO.enable_w1tc |= (0x1 << PIN_nTRST);
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GPIO.pin[PIN_nRESET].driver = 0;
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GPIO.enable_w1tc |= (0x1 << PIN_nRESET);
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}
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// SWCLK/TCK I/O pin -------------------------------------
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/**
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* @brief SWCLK/TCK I/O pin: Get Input.
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*
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* @return Current status of the SWCLK/TCK DAP hardware I/O pin.
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*/
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__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
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{
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////TODO: can we set to 0?
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return 0;
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}
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/**
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* @brief SWCLK/TCK I/O pin: Set Output to High.
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*
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* Set the SWCLK/TCK DAP hardware I/O pin to high level.
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*/
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__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
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{
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GPIO.out_w1ts |= (0x1 << PIN_SWCLK);
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}
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/**
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* @brief SWCLK/TCK I/O pin: Set Output to Low.
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*
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* Set the SWCLK/TCK DAP hardware I/O pin to low level.
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*/
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__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
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{
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GPIO.out_w1tc |= (0x1 << PIN_SWCLK);
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}
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// SWDIO/TMS Pin I/O --------------------------------------
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/**
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* @brief SWDIO/TMS I/O pin: Get Input.
|
|
*
|
|
* @return Current status of the SWDIO/TMS DAP hardware I/O pin.
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
|
|
{
|
|
return ((GPIO.in >> PIN_SWDIO) & 0x1) ? 1 : 0;
|
|
}
|
|
|
|
/**
|
|
* @brief SWDIO/TMS I/O pin: Set Output to High.
|
|
*
|
|
* Set the SWDIO/TMS DAP hardware I/O pin to high level.
|
|
*/
|
|
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
|
|
{
|
|
GPIO.out_w1ts |= (0x1 << PIN_SWDIO_MOSI);
|
|
}
|
|
|
|
/**
|
|
* @brief SWDIO/TMS I/O pin: Set Output to Low.
|
|
*
|
|
* Set the SWDIO/TMS DAP hardware I/O pin to low level.
|
|
*/
|
|
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
|
|
{
|
|
GPIO.out_w1tc |= (0x1 << PIN_SWDIO_MOSI);
|
|
}
|
|
|
|
/**
|
|
* @brief SWDIO I/O pin: Get Input (used in SWD mode only).
|
|
*
|
|
* @return Current status of the SWDIO DAP hardware I/O pin.
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
|
|
{
|
|
return ((GPIO.in >> PIN_SWDIO) & 0x1) ? 1 : 0;
|
|
}
|
|
|
|
/**
|
|
* @brief SWDIO I/O pin: Set Output (used in SWD mode only).
|
|
*
|
|
* @param bit Output value for the SWDIO DAP hardware I/O pin.
|
|
*
|
|
*/
|
|
__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
|
|
{
|
|
/**
|
|
* Important: Use only one bit (bit0) of param!
|
|
* Sometimes the func "SWD_TransferFunction" of SW_DP.c will
|
|
* issue "2" as param instead of "0". Zach Lee
|
|
*/
|
|
if ((bit & 1U) == 1)
|
|
{
|
|
//set bit
|
|
GPIO.out_w1ts |= (0x1 << PIN_SWDIO_MOSI);
|
|
|
|
}
|
|
else
|
|
{
|
|
//reset bit
|
|
GPIO.out_w1tc |= (0x1 << PIN_SWDIO_MOSI);
|
|
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
|
|
* Configure the SWDIO DAP hardware I/O pin to output mode. This function is
|
|
* called prior \ref PIN_SWDIO_OUT function calls.
|
|
*/
|
|
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
|
|
{
|
|
// Need fast response
|
|
//// TODO: low speed
|
|
// set \ref gpio_set_direction -> OUTPUT
|
|
// GPIO.enable_w1ts |= (0x1 << PIN_SWDIO_MOSI);
|
|
// GPIO.pin[PIN_SWDIO_MOSI].driver = 0;
|
|
do {}while (0);
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
|
|
* Configure the SWDIO DAP hardware I/O pin to input mode. This function is
|
|
* called prior \ref PIN_SWDIO_IN function calls.
|
|
*/
|
|
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
|
|
{
|
|
// Need fast response
|
|
// set \ref gpio_set_dircetion -> INPUT
|
|
// esp8266 input is always connected
|
|
// GPIO.enable_w1tc |= (0x1 << PIN_SWDIO_MOSI);
|
|
// GPIO.pin[PIN_SWDIO_MOSI].driver = 0;
|
|
GPIO.out_w1ts |= (0x1 << PIN_SWDIO_MOSI);
|
|
}
|
|
|
|
// TDI Pin I/O ---------------------------------------------
|
|
|
|
/**
|
|
* @brief TDI I/O pin: Get Input.
|
|
*
|
|
* @return Current status of the TDI DAP hardware I/O pin.
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
|
|
{
|
|
return ((GPIO.in >> PIN_TDI) & 0x1) ? 1 : 0;
|
|
}
|
|
|
|
/**
|
|
* @brief TDI I/O pin: Set Output.
|
|
*
|
|
* @param bit Output value for the TDI DAP hardware I/O pin.
|
|
*
|
|
*/
|
|
__STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
|
|
{
|
|
if ((bit & 1U) == 1)
|
|
{
|
|
//set bit
|
|
GPIO.out_w1ts |= (0x1 << PIN_TDI);
|
|
|
|
}
|
|
else
|
|
{
|
|
//reset bit
|
|
GPIO.out_w1tc |= (0x1 << PIN_TDI);
|
|
|
|
}
|
|
}
|
|
|
|
// TDO Pin I/O ---------------------------------------------
|
|
|
|
/**
|
|
* @brief TDO I/O pin: Get Input.
|
|
*
|
|
* @return Current status of the TDO DAP hardware I/O pin.
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
|
|
{
|
|
return ((GPIO.in >> PIN_TDO) & 0x1) ? 1 : 0;
|
|
}
|
|
|
|
// nTRST Pin I/O -------------------------------------------
|
|
|
|
/**
|
|
* @brief nTRST I/O pin: Get Input.
|
|
*
|
|
* @return Current status of the nTRST DAP hardware I/O pin.
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
|
|
{
|
|
return 0; // not available
|
|
}
|
|
|
|
/**
|
|
* @brief nTRST I/O pin: Set Output.
|
|
*
|
|
* @param bit JTAG TRST Test Reset pin status:
|
|
* - 0: issue a JTAG TRST Test Reset.
|
|
- 1: release JTAG TRST Test Reset.
|
|
*/
|
|
__STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
|
|
{
|
|
// Vendor reset sequence
|
|
; // not available
|
|
}
|
|
|
|
// nRESET Pin I/O------------------------------------------
|
|
|
|
/**
|
|
* @brief nRESET I/O pin: Get Input.
|
|
*
|
|
* @return Current status of the nRESET DAP hardware I/O pin.
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
|
|
{
|
|
return ((GPIO.in >> PIN_nRESET) & 0x1) ? 1 : 0;
|
|
}
|
|
|
|
/**
|
|
* @brief nRESET I/O pin: Set Output.
|
|
*
|
|
* @param bit target device hardware reset pin status:
|
|
* - 0: issue a device hardware reset.
|
|
* - 1: release device hardware reset.
|
|
*/
|
|
__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
|
|
{
|
|
// Vendor reset sequence
|
|
//// FIXME: unavailable
|
|
if ((bit & 1U) == 1)
|
|
{
|
|
//set bit
|
|
GPIO.out_w1ts |= (0x1 << PIN_nRESET);
|
|
}
|
|
else
|
|
{
|
|
//reset bit
|
|
GPIO.out_w1tc |= (0x1 << PIN_nRESET);
|
|
}
|
|
}
|
|
|
|
///@}
|
|
|
|
//**************************************************************************************************
|
|
/**
|
|
\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
|
|
\ingroup DAP_ConfigIO_gr
|
|
@{
|
|
|
|
CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
|
|
|
|
It is recommended to provide the following LEDs for status indication:
|
|
- Connect LED: is active when the DAP hardware is connected to a debugger.
|
|
- Running LED: is active when the debugger has put the target device into running state.
|
|
*/
|
|
|
|
/** Debug Unit: Set status of Connected LED.
|
|
\param bit status of the Connect LED.
|
|
- 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
|
|
- 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
|
|
*/
|
|
|
|
/**
|
|
* @brief Debug Unit: Set status of Connected LED.
|
|
*
|
|
* @param bit status of the Connect LED.
|
|
* - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
|
|
* - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
|
|
*/
|
|
__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
|
|
{
|
|
if (bit)
|
|
{
|
|
//set bit
|
|
GPIO.out_w1ts |= (0x1 << PIN_LED_CONNECTED);
|
|
}
|
|
else
|
|
{
|
|
//reset bit
|
|
GPIO.out_w1tc |= (0x1 << PIN_LED_CONNECTED);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Debug Unit: Set status Target Running LED.
|
|
*
|
|
* @param bit status of the Target Running LED.
|
|
* - 1: Target Running LED ON: program execution in target started.
|
|
* - 0: Target Running LED OFF: program execution in target stopped.
|
|
*/
|
|
__STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
|
|
{
|
|
if (bit)
|
|
{
|
|
//set bit
|
|
GPIO.out_w1ts |= (0x1 << PIN_LED_RUNNING);
|
|
}
|
|
else
|
|
{
|
|
//reset bit
|
|
GPIO.out_w1tc |= (0x1 << PIN_LED_RUNNING);
|
|
}
|
|
}
|
|
|
|
///@}
|
|
|
|
//**************************************************************************************************
|
|
/**
|
|
\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
|
|
\ingroup DAP_ConfigIO_gr
|
|
@{
|
|
Access function for Test Domain Timer.
|
|
|
|
The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
|
|
default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
|
|
|
|
*/
|
|
|
|
/**
|
|
* @brief Get timestamp of Test Domain Timer.
|
|
*
|
|
* @return Current timestamp value.
|
|
*/
|
|
__STATIC_INLINE uint32_t TIMESTAMP_GET(void)
|
|
{
|
|
// FRC1 is a 23-bit countdown timer
|
|
return (0x7FFFFF - (frc1.count.data));
|
|
}
|
|
|
|
///@}
|
|
|
|
//**************************************************************************************************
|
|
/**
|
|
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
|
|
\ingroup DAP_ConfigIO_gr
|
|
@{
|
|
|
|
CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
|
|
*/
|
|
|
|
/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
|
|
This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
|
|
Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
|
|
- I/O clock system enabled.
|
|
- all I/O pins: input buffer enabled, output pins are set to HighZ mode.
|
|
- for nTRST, nRESET a weak pull-up (if available) is enabled.
|
|
- LED output pins are enabled and LEDs are turned off.
|
|
*/
|
|
__STATIC_INLINE void DAP_SETUP(void)
|
|
{
|
|
DAP_SPI_Init();
|
|
DAP_SPI_Disable();
|
|
|
|
|
|
// This function maybe unnecessary...
|
|
// gpio_set_direction(PIN_SWCLK, GPIO_MODE_DEF_INPUT);
|
|
// gpio_set_direction(PIN_SWDIO, GPIO_MODE_DEF_INPUT); //
|
|
gpio_set_direction(PIN_nRESET, GPIO_MODE_DEF_INPUT); //
|
|
gpio_set_direction(PIN_TDI, GPIO_MODE_DEF_INPUT);
|
|
gpio_set_direction(PIN_TDO, GPIO_MODE_DEF_INPUT);
|
|
|
|
// Configure: LED as output (turned off)
|
|
gpio_set_direction(PIN_LED_CONNECTED, GPIO_MODE_DEF_OUTPUT);
|
|
LED_CONNECTED_OUT(0);
|
|
gpio_set_direction(PIN_LED_RUNNING, GPIO_MODE_DEF_OUTPUT);
|
|
LED_RUNNING_OUT(0);
|
|
|
|
PORT_OFF();
|
|
}
|
|
|
|
/** Reset Target Device with custom specific I/O pin or command sequence.
|
|
This function allows the optional implementation of a device specific reset sequence.
|
|
It is called when the command \ref DAP_ResetTarget and is for example required
|
|
when a device needs a time-critical unlock sequence that enables the debug port.
|
|
\return 0 = no device specific reset sequence is implemented.\n
|
|
1 = a device specific reset sequence is implemented.
|
|
*/
|
|
__STATIC_INLINE uint8_t RESET_TARGET(void)
|
|
{
|
|
return (0U); // not available
|
|
}
|
|
|
|
///@}
|
|
|
|
#endif /* __DAP_CONFIG_H__ */
|