158 lines
4.2 KiB
C
158 lines
4.2 KiB
C
/**
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* @file spi_switch.c
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* @author windowsair
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* @brief Switching between SPI mode and IO mode
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* @version 0.1
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* @date 2020-11-25
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*
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* @copyright Copyright (c) 2020
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*
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*/
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#include <stdbool.h>
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#include "esp8266/spi_struct.h"
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#include "esp8266/pin_mux_register.h"
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#include "esp8266/gpio_struct.h"
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#include "cmsis_compiler.h"
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#include "spi_switch.h"
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#define DAP_SPI SPI1
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#define ENTER_CRITICAL() portENTER_CRITICAL()
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#define EXIT_CRITICAL() portEXIT_CRITICAL()
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typedef enum {
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SPI_40MHz_DIV = 2,
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// SPI_80MHz_DIV = 1, //// FIXME: high speed clock
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} spi_clk_div_t;
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/**
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* @brief Initialize on first use
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*
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*/
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void DAP_SPI_Init()
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{
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// Disable flash operation mode
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DAP_SPI.user.flash_mode = false;
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// Set to Master mode
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DAP_SPI.pin.slave_mode = false;
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DAP_SPI.slave.slave_mode = false;
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// Master uses the entire hardware buffer to improve transmission speed
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// If the following fields are enabled, only a part of the buffer is used
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DAP_SPI.user.usr_mosi_highpart = false;
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DAP_SPI.user.usr_miso_highpart = false;
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// Disable cs pin
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DAP_SPI.user.cs_setup = false;
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DAP_SPI.user.cs_hold = false;
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// Duplex transmit
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DAP_SPI.user.duplex = true;
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// SCLK delay setting
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DAP_SPI.user.ck_i_edge = true;
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DAP_SPI.ctrl2.mosi_delay_num = 0;
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DAP_SPI.ctrl2.miso_delay_num = 0;
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// DIO & QIO SPI disable
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DAP_SPI.user.fwrite_dual = false;
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DAP_SPI.user.fwrite_quad = false;
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DAP_SPI.user.fwrite_dio = false;
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DAP_SPI.user.fwrite_qio = false;
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DAP_SPI.ctrl.fread_dual = false;
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DAP_SPI.ctrl.fread_quad = false;
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DAP_SPI.ctrl.fread_dio = false;
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DAP_SPI.ctrl.fread_qio = false;
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DAP_SPI.ctrl.fastrd_mode = true;
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// Enable soft reset
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DAP_SPI.slave.sync_reset = true;
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// Set the clock polarity and phase CPOL = CPHA = 0
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DAP_SPI.pin.ck_idle_edge = 1; // HIGH while idle
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DAP_SPI.user.ck_out_edge = 0;
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// Set data bit order
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DAP_SPI.ctrl.wr_bit_order = 1; // SWD -> LSB
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DAP_SPI.ctrl.rd_bit_order = 1; // SWD -> LSB
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// Set data byte order
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DAP_SPI.user.wr_byte_order = 0; // SWD -> litte_endian && Risc V -> litte_endian
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DAP_SPI.user.rd_byte_order = 0; // SWD -> litte_endian && Risc V -> litte_endian
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// Set dummy
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DAP_SPI.user.usr_dummy = 0;
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// Initialize HSPI IO
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gpio_pin_reg_t pin_reg;
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, FUNC_HSPI_CLK); // GPIO14 is SPI CLK pin (Clock)
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GPIO.enable_w1ts |= (0x1 << 14); // PP Output
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(14));
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pin_reg.pullup = 1;
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WRITE_PERI_REG(GPIO_PIN_REG(14), pin_reg.val);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_HSPID_MOSI); // GPIO13 is SPI MOSI pin (Master Data Out)
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GPIO.enable_w1ts |= (0x1 << 13);
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GPIO.pin[13].driver = 0; // PP Output or OD output
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(13));
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pin_reg.pullup = 0;
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WRITE_PERI_REG(GPIO_PIN_REG(13), pin_reg.val);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, FUNC_HSPIQ_MISO); // GPIO12 is SPI MISO pin (Master Data In)
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// esp8266 in is always connected
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(12));
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pin_reg.pullup = 0;
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WRITE_PERI_REG(GPIO_PIN_REG(12), pin_reg.val);
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// Set spi clk div
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CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI1_CLK_EQU_SYS_CLK);
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DAP_SPI.clock.clk_equ_sysclk = false;
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DAP_SPI.clock.clkdiv_pre = 0;
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DAP_SPI.clock.clkcnt_n = SPI_40MHz_DIV - 1;
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DAP_SPI.clock.clkcnt_h = SPI_40MHz_DIV / 2 - 1;
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DAP_SPI.clock.clkcnt_l = SPI_40MHz_DIV - 1;
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// Do not use command and addr
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DAP_SPI.user.usr_command = 0;
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DAP_SPI.user.usr_addr = 0;
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}
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/**
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* @brief Use SPI acclerate
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*
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*/
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void DAP_SPI_Enable()
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{
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_HSPID_MOSI); // GPIO13 is SPI MOSI pin (Master Data Out)
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}
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/**
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* @brief Disable SPI
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*
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*/
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__FORCEINLINE void DAP_SPI_Disable()
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{
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DAP_SPI_Deinit();
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}
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__FORCEINLINE void DAP_SPI_Deinit()
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{
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CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_MTCK_U, (PERIPHS_IO_MUX_FUNC << PERIPHS_IO_MUX_FUNC_S));
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// may be unuse
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gpio_pin_reg_t pin_reg;
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GPIO.enable_w1ts |= (0x1 << 13);
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GPIO.pin[13].driver = 0; // OD Output
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pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(13));
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pin_reg.pullup = 1;
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WRITE_PERI_REG(GPIO_PIN_REG(13), pin_reg.val);
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} |